====== Post Route Write Verilog ======

Write verilog for STA:

<code tcl>
set dir .
set topLevel zx211000_htm
set version 0818_1320

###### Name changes 
## using icc native command (extra rule for some LSI legacy tools)
define_name_rules verilog -case_insensitive
change_names -hierarchy -rules verilog -verbose
write_verilog -no_unconnected_cells ${dir}/${topLevel}.${version}.v
</code>