====== PrimeTime STA Flow ======
===== Flow Chart =====


{{:vlsi:pt:sta-flow.png|}}

===== Sample Script =====

<code tcl>

#-@@- File name : pt_flow.tcl
#-@@- Created by YaoQiang
#-@@- This file is to set STA flow.
#-@@- ----------------------------------------- 
#-@@- -----------------------------------------
#-@@- stage  | prelayout/postlayout
#-@@- mode   | func/scan/mbist/mbisr/power
#-@@- corner | max/min/maxlt/minht
#-@@- ------------------------------------------
#+++++++++++++++++++++++++++++++++++++++++++++++
#-@@- prelayout netlist :
#-@@- /home/l8a0492s/proj_data/${phase}/verilog
#+++++++++++++++++++++++++++++++++++++++++++++++
#-@@- postlayout netlist :
#-@@- ../../release/postlayout
#-@@- ../../release/extract
#+++++++++++++++++++++++++++++++++++++++++++++++
#-@@- sdc files :
#-@@- ./sdc
#+++++++++++++++++++++++++++++++++++++++++++++++

set topLevel zx211000_htm
set phase FDH

set RootDir /home/l8a0492s/proj_data/${phase}

if {![info exists checkRamp]} {
  set checkRamp 1
}

if {![info exists stage]} {
  set stage postlayout
}

if {![info exists mode]} {
  set mode power
}
if {![info exists corner]} {
  set corner maxlt
}

if {[regexp power $mode]} {
  set corner max
  #-@@- set corner minht
}

if {[regexp power $mode]} {
  set RELEASE "/home/l8a0492s_2/release/power"
} else {
  if {[file exists ./release]} {
	echo ">> Read RELEASE directory from ./release"
	set RELEASE "./release"
  } else {
    set RELEASE "/home/l8a0492s_4/release"
  }
}
set verilog [glob -directory "${RELEASE}/postlayout" -type file *.v]

set search_path ". ${RootDir}/db_ccs"

set LSI_RELEASE [getenv LSI_RELEASE]

#-@@-Library setup and spef file specified. 
if {$corner == "max"} {
  source ${RootDir}/linkScripts/set_max_link_library.tcl
  set keywd cworst_125	
  set pvt lsiW_090V_125C
} elseif {$corner == "min"} {
  source ${RootDir}/linkScripts/set_min_link_library.tcl
  set keywd cbest_m40
  set pvt lsiB_105V_m40C
} elseif {$corner == "maxlt"} {
  source ${RootDir}/linkScripts/set_maxOff_link_library.tcl
  set keywd cworst_m40
  set pvt lsiW_090V_m40C
} elseif {$corner == "minht"} {
  source ${RootDir}/linkScripts/set_minOff_link_library.tcl
  set keywd cbest_125
  set pvt lsiB_105V_125C
} elseif {$corner == "rcmax"} {
  source ${RootDir}/linkScripts/set_max_link_library.tcl
  set keywd rcworst_125	
  set pvt lsiW_090V_125C
} elseif {$corner == "rcmin"} {
  source ${RootDir}/linkScripts/set_min_link_library.tcl
  set keywd rcbest_m40
  set pvt lsiB_105V_m40C
}
  
set rc_files [glob -tail -directory ${RELEASE}/extract *_${keywd}.spef.gz]
source scripts/lib.addon.tcl

#-@@-Select the timing constraint for different modes.
if {[regexp prelayout $stage]} {
  set margin 0.75
} else {
  set margin 1.00 
}

if {![file exists sdc]} {
  file link sdc ${RELEASE}/sdc
}
source sdc/zx211000.project_default.tcl

if {$mode == "func" || $mode == "power" } {
  set sdc sdc/${topLevel}.func.tcl
} elseif {$mode == "scan"} {
  set sdc sdc/${topLevel}.scan_shift.tcl
} elseif {$mode == "mbist"} {
  set sdc sdc/${topLevel}.mbist.tcl
} elseif {$mode == "bisr"} {
  set sdc sdc/${topLevel}.bisr.tcl
} else {
  error "None one of func or scan or mbist or mbisr mode are defined, exit"
}
#
set version ${stage}_${mode}_${corner}
set rpt_dir ${version}
if {![file isdirectory $rpt_dir]} {
  file mkdir ${rpt_dir}
}

#-@@- Sep.15,2010 Netlist and spef version record
sh ls -ltr ${RELEASE}/extract/*.gz > ${rpt_dir}/version
sh echo "" >> ${rpt_dir}/version
sh ls -ltr ${RELEASE}/postlayout/*.v >> ${rpt_dir}/version

#-@@- Read cw108032 & DDR
#read_verilog /home/l8a0492s_2/release/FDH0/verilog/cw108032_8rx8tx_1_5.v
foreach v [glob -directory /home/l8a0492s_2/release/verilog *.v] {
  read_verilog $v
}

## cw108032_8rx8tx_1_5.v netlist has been updated, i use old netlist as temp version.



#-@@- Read LBRAM 
foreach lbv [glob -directory /home/l8a0492s/proj_data/FDH/lbrNetlist *.v] {
  read_verilog $lbv
}

foreach v $verilog {
  read_verilog $v
}
current_design $topLevel
#
puts "Linking design $topLevel"
link_design -verbose -keep_sub_designs > ${rpt_dir}/${topLevel}_link.rpt
current_design $topLevel
#
### Check the design to make sure it linked, exit if design doesn't link
set input_file_id  [open ${rpt_dir}/${topLevel}_link.rpt r]
while { [gets $input_file_id line] >= 0 } {
  if { [regexp "^Warning: Unable to resolve reference|^Error" $line] } {
    puts "Error: design link failed. Aborting .... "
    #-@@- quit
  }
}
close $input_file_id
#
list_libraries -only_used >> ${rpt_dir}/${topLevel}_link.rpt
#
if {[regexp prelayout $stage]}  {
  source ${RootDir}/linkScripts/set_max_min_library.tcl
  set_operating_condition -analysis_type on_chip_variation \
    -max_library g65xp_lsiW_090V_125C.db:g65xp \
    -max lsiW_090V_125C \
    -min_library g65xp_lsiB_105V_m40C.db:g65xp \
    -min lsiB_105V_m40C
} else {
  remove_operating_condition
  set_operating_conditions -analysis_type on_chip_variation \
    -max_library g65xp_${pvt}.db:g65xp -max ${pvt} \
    -min_library g65xp_${pvt}.db:g65xp -min ${pvt}
}
#-@@- Aug.20,2010
set auto_wire_load_selection false
set_wire_load_mode top

source -echo -verbose ${sdc} > ${rpt_dir}/sdc.${version}.log

#----------------------------------------------------------
# Disable LBRAM timing arcs ( write through ) Sep.2,2010
#----------------------------------------------------------
set all_pld2t2qnd [get_cells -hierarchical * -filter "ref_name =~ PLD2T2QNXP"]

foreach_in_collection my_pld2t2qnd $all_pld2t2qnd {
  set_disable_timing -from G0  -to QN $my_pld2t2qnd
  set_disable_timing -from GN0 -to QN $my_pld2t2qnd
  set_disable_timing -from G1  -to QN $my_pld2t2qnd
  set_disable_timing -from GN1 -to QN $my_pld2t2qnd
  set_disable_timing -from D   -to QN $my_pld2t2qnd
}

suppress_message UITE-216
if { 0 && [file exists scripts/group_path.addon.tcl] } {
  source -echo -verbose scripts/group_path.addon.tcl > ${rpt_dir}/group_path.${version}.log
}
unsuppress_message UITE-216

if {![regexp prelayout $stage]} {
  source scripts/ptsi_g65.tcl
  if { ![regexp power $mode] } {
    source scripts/ptsi_g65_noise.tcl
  }
}

#-@@- to disable IO timing
#-@@- !!!!!! Using ZTE constraint for IO checks
#-@@- !!!!!! set_false_path -from [all_inputs]
#-@@- !!!!!! set_false_path -to [all_outputs]

#-@@- Oct.12,2010 for DDR DCD check
remove_annotated_parasitics [all_connected [get_pins u_PLL_DDR/pll/CKOUT]]

update_timing
if {![regexp prelayout $stage]} {
  set rtopt "-derate -cross -tran -cap -input"
} else {
  set rtopt "-tran"
}

if {[file exists scripts/pt_pba.tcl]} {
  source scripts/pt_pba.tcl
  set rtopt "-derate -cross -net -tran -cap -input -pba_mode path -slack_lesser 0"
}


if {[regexp power $mode]} {
  source /lsi/soft/lsi/fs/5.0/lsi_fs_5.0/bin/Linux-RH-EL3.0/lsitkdelaydataViolation.tcl
  set timing_save_pin_arrival_and_slack true
  set timing_save_arrival_window_and_slack true
  createLsiTkDelayData -tech g65p -metal_layer 6+2 -delay max -gzip -power_only
  write_sdc -version 1.6 ${topLevel}.sdc
}

save_session ${rpt_dir}/session -replace

if {![regexp power $mode]} {
  #-@@- reports
  eval "report_timing -group main_clk -delay max -max 5000 -sig 3 ${rtopt} > ${rpt_dir}/setup.main_clk.pba.rpt"
  eval "report_timing -group main_clk -delay min -max 5000 -sig 3 ${rtopt} > ${rpt_dir}/hold.main_clk.pba.rpt"
  eval "report_timing -group *async* -delay min -max 5000 -sig 3 ${rtopt} > ${rpt_dir}/hold.async.pba.rpt"
  eval "report_timing -group EJClk -delay min -max 5000 -sig 3 ${rtopt} > ${rpt_dir}/hold.EJClk.pba.rpt"
  eval "report_timing -group gclk_main123 -delay max -max 5000 -sig 3 ${rtopt} > ${rpt_dir}/setup.g123.pba.rpt"
  eval "report_timing -group gclk_main123 -delay min -max 5000 -sig 3 ${rtopt} > ${rpt_dir}/hold.g123.pba.rpt"
  eval "report_timing -pba exhaustive -slack_lesser 0.0 -max 100 -path summary > ${rpt_dir}/setup.pba.summary"
  eval "report_timing -pba exhaustive -slack_lesser 0.0 -max 100 -path summary -delay min > ${rpt_dir}/hold.pba.summary"

  report_qor > ${rpt_dir}/qor.${rpt_dir}
  write_stat

  #source scripts/pt.alias.tcl
  #source scripts/path_summary.tcl
  report_constraint -all_vio > ${rpt_dir}/all_vio.rpt
  report_constraint -all_vio -verbose > ${rpt_dir}/all_vio.verbose.rpt
  
  report_constraints -all_vio -max_delay -min_delay -max_capacitance -recovery -removal -clock_gating_setup -clock_gating_hold  >  ${rpt_dir}/all_violators.rpt
   
  report_constraint -all_vio -max_transition -no > ${rpt_dir}/max_tran.vio
  sh grep -v u_cw108032_8rx8tx_1_5_wrapper ${rpt_dir}/max_tran.vio > max_tran.${corner}.vio
  sh mv -f max_tran.${corner}.vio ${rpt_dir}/max_tran.noSerDes.vio
}

if { 0 && [file exists scripts/synchronizer.tcl] && [file exists scripts/synchronizer.ZTE.list]} {
  source -echo scripts/synchronizer.tcl 
}

if {$checkRamp} {
  if {$corner != "rcmax" || $corner!= "rcmin"} {
    #-@@- Please enable following two lines if need to check DDR timing.
    #-@@- source scripts/ddrchecks/ddr.wrapper.tcl
    #-@@- source scripts/ddrchecks/ddrchecks.tcl
    if {[file exists scripts/ramptime.tcl]} {
  	  source -echo scripts/ramptime.tcl
    }
  }
}

source -echo /home/ztzx2110002v0/users/dongu/FDH1/sta/scripts/pt_report.tcl
#source -echo /home/ztzx2110002v0/users/dongu/FDH1/sta/scripts/pt_sdf_g65.tcl

# if { [string compare $corner "minht"] == 0 } { 
#    source -echo scripts/signalEM.tcl
#    source -echo scripts/cellEM.tcl
# }

quit
</code>