_query_db
add_clock_drivers
add_distributed_hosts
add_drc_error_detail
add_end_cap
add_open_drc_error_detail
add_pg_pin_to_db
add_pg_pin_to_lib
add_port_state
add_pst_state
add_row
add_tap_cell_array
add_to_collection
add_to_rp_group
adjust_fp_floorplan
adjust_fp_io_placement
adjust_premesh_connection
after
alias
align_fp_pins
align_objects
all_active_scenarios
all_ao_cells
all_bounds_of_cell
all_cells_in_bound
all_clocks
all_connected
all_connectivity_fanin
all_connectivity_fanout
all_critical_cells
all_critical_pins
all_designs
all_dont_touch
all_drc_violated_nets
all_fanin
all_fanout
all_fixed_placement
all_high_fanout
all_ideal_nets
all_inputs
all_isolation_cells
all_level_shifters
all_macro_cells
all_mtcmos_cells
all_objects_in_bounding_box
all_outputs
all_physical_only_cells
all_physical_only_nets
all_physical_only_ports
all_registers
all_rp_groups
all_rp_hierarchicals
all_rp_inclusions
all_rp_instantiations
all_rp_references
all_scenarios
all_size_only_cells
all_spare_cells
all_threestate
all_tieoff_cells
allocate_fp_budgets
analyze_fp_rail
analyze_fp_routing
analyze_rail
analyze_subcircuit
append
append_to_collection
apropos
archive_design
array
assign_flip_chip_nets
balance_inter_clock_delay
binary
break
calculate_caa_based_yield2db
calculate_hier_antenna_property
catch
cd
change_fp_soft_macro_to_black_box
change_link
change_macro_view
change_names
change_selection
change_selection_no_core
change_selection_too_many_objects
change_tie_connection
characterize
check_clock_tree
check_database
check_design
check_error
check_fp_budget_result
check_fp_pin_alignment
check_fp_pin_assignment
check_fp_rail
check_fp_timing_environment
check_isolation_cells
check_legality
check_level_shifters
check_library
check_license
check_mesh_net
check_mpc
check_mv_design
check_noise
check_physical_constraints
check_physical_design
check_route
check_routeability
check_rp_groups
check_scan_chain
check_scenarios
check_target_library_subset
check_timing
check_tlu_plus_files
clock
clock_opt
close
close_distributed_route
close_mw_cel
close_mw_lib
collection_to_list
commit_fp_group_block_ring
commit_fp_plan_groups
commit_fp_rail
commit_skew_group
compare_collections
compare_delay_calculation
compare_interface_timing
compare_lib
compare_rc
compile_clock_tree
compile_fp_clock_plan
compile_premesh_tree
compute_polygons
concat
connect_net
connect_pin
connect_power_switch
connect_spare_diode
connect_supply_net
connect_tie_cells
continue
convert_from_polygon
convert_mw_lib
convert_to_polygon
convert_wire_ends
convert_wire_to_pin
copy_collection
copy_floorplan
copy_mim
copy_mw_cel
copy_mw_lib
copy_objects
count_drc_violations
cputime
create_auto_shield
create_base_array
create_boundary
create_bounds
create_buffer_tree
create_cell
create_clock
create_clock_mesh
create_command_group
create_connview
create_differential_group
create_drc_error
create_drc_error_type
create_edit_group
create_fp_block_shielding
create_fp_blockages_for_child_hardmacro
create_fp_group_block_ring
create_fp_pins
create_fp_placement
create_fp_plan_group_padding
create_fp_virtual_pad
create_generated_clock
create_ilm
create_ilm_models
create_lib_track
create_macro_fram
create_mw_cel
create_mw_lib
create_net
create_net_shape
create_open_drc_error
create_open_locator_drc_error
create_operating_conditions
create_pad_rings
create_partition
create_pg_network
create_physical_bus
create_physical_buses_from_patterns
create_pin_guide
create_placement
create_placement_blockage
create_plan_groups
create_port
create_power_domain
create_power_straps
create_power_switch
create_power_switch_array
create_power_switch_ring
create_preroute_vias
create_pst
create_qor_snapshot
create_qtm_clock
create_qtm_constraint_arc
create_qtm_delay_arc
create_qtm_drive_type
create_qtm_generated_clock
create_qtm_insertion_delay
create_qtm_load_type
create_qtm_model
create_qtm_path_type
create_qtm_port
create_rail_setup
create_rectangular_rings
create_rectilinear_rings
create_route_guide
create_routing_blockage
create_rp_group
create_scenario
create_short_drc_error
create_site_row
create_spacing_drc_error
create_stack_via_on_pad_pin
create_supply_net
create_supply_port
create_terminal
create_text
create_track
create_user_shape
create_via
create_voltage_area
create_zrt_shield
current_design
current_design_name
current_instance
current_mw_cel
current_mw_lib
current_scenario
cut_objects
cut_row
date
decrypt_lib
define_antenna_accumulation_mode
define_antenna_area_rule
define_antenna_layer_ratio_scale
define_antenna_layer_rule
define_antenna_rule
define_bus
define_io_antenna_area
define_io_diode_protection
define_io_gate_size
define_name_rules
define_proc_attributes
define_routing_rule
define_scaling_lib_group
define_user_attribute
define_via
define_zrt_redundant_vias
delete_operating_conditions
derive_constraints
derive_mpc_macro_options
derive_mpc_options
derive_mpc_port_options
derive_pg_connection
detect_flcc_hotspot
detect_lcc_hotspot
disconnect_net
display_flip_chip_route_flylines
distribute_objects
drive_of
echo
eco_netlist
encoding
end_fp_trace_mode
eof
error
error_info
estimate_fp_area
estimate_fp_black_boxes
estimate_rc
eval
exec
exit
expand_flip_chip_cell_locations
expand_objects
explore_power_switch
expr
extract_blockage_pin_via
extract_flcc_hotspot
extract_fp_rail_to_constraints
extract_fp_relative_location
extract_hier_antenna_property
extract_rc
extract_rp_group
extract_zrt_hier_antenna_property
fblocked
fconfigure
fcopy
file
fileevent
filter_collection
fix_flcc_hotspot
fix_isolated_via
fix_lcc_hotspot
flatten_clock_gating
flatten_fp_black_boxes
flatten_fp_hierarchy
flip_mim
flip_objects
flush
focal_opt
for
foreach
foreach_in_collection
format
generate_qtm_model
get_adjusted_endpoints
get_alternative_lib_cells
get_always_on_logic
get_app_var
get_attribute
get_bounds
get_buffers
get_cell_sites
get_cells
get_clocks
get_command_option_values
get_core_area
get_coupling_capacitors
get_cts_scenario
get_design_lib_path
get_designs
get_die_area
get_dominant_scenarios
get_drc_errors
get_edit_groups
get_error_view_property
get_flat_cells
get_flat_nets
get_flat_pins
get_floorplan_data
get_fp_trace_mode
get_fp_wirelength
get_generated_clocks
get_ilm_objects
get_ilms
get_layer_attribute
get_layers
get_lib_attribute
get_lib_cells
get_lib_pins
get_libs
get_license
get_location
get_magnet_cells
get_mesh_nets
get_message_info
get_mw_cels
get_net_shapes
get_nets
get_new_bounds
get_object_fixed_edit
get_object_name
get_object_snap_type
get_path_groups
get_physical_buses
get_physical_lib_cells
get_physical_lib_pins
get_physical_libs
get_pin_guides
get_pin_shapes
get_pins
get_placement_area
get_placement_blockages
get_plan_groups
get_polygon_area
get_ports
get_power_domains
get_power_switches
get_route_guides
get_route_mode_options
get_route_zrt_common_options
get_route_zrt_detail_options
get_route_zrt_global_options
get_route_zrt_track_options
get_routing_blockages
get_rp_group_keepouts
get_rp_groups
get_scan_cells_of_chain
get_scan_chains
get_selection
get_si_xtalk_bumps
get_site_rows
get_supply_nets
get_supply_ports
get_terminals
get_text
get_timing_paths
get_tracks
get_unix_variable
get_user_grid
get_user_shapes
get_via_masters
get_vias
get_voltage_areas
get_zero_interconnect_delay_mode
get_zrt_net_properties
getenv
gets
glob
global
group
group_path
gui_bin
gui_change_highlight
gui_create_attrdef
gui_create_attrgroup
gui_create_pref_category
gui_create_pref_key
gui_create_vm
gui_create_vm_objects
gui_create_vmbucket
gui_delete_attrdef
gui_delete_attrgroup
gui_edit_vmbucket_contents
gui_exist_pref_category
gui_exist_pref_key
gui_get_current_task
gui_get_highlight
gui_get_highlight_options
gui_get_pref_keys
gui_get_pref_value
gui_get_routes_between_objects
gui_get_setting
gui_get_task_list
gui_get_vm
gui_get_vmbucket
gui_get_window_ids
gui_get_window_pref_categories
gui_get_window_pref_keys
gui_get_window_pref_value
gui_get_window_types
gui_list_attrdefs
gui_list_attrgroups
gui_list_vm
gui_load_cell_density_mm
gui_load_pin_density_mm
gui_remove_pref_key
gui_remove_vm
gui_remove_vmbucket
gui_set_current_task
gui_set_highlight_options
gui_set_pref_value
gui_set_setting
gui_set_vm
gui_set_vmbucket
gui_set_window_pref_key
gui_show_man_page
gui_start
gui_stop
gui_update_attrdef
gui_update_attrgroup
gui_update_pref_file
gui_update_vm
gui_update_vm_annotations
help
history
hookup_retention_register
hookup_testports
identify_clock_gating
if
ignore_site_row
import_designs
import_fp_black_boxes
incr
index_collection
info
initialize_floorplan
initialize_rectilinear_block
insert_buffer
insert_diode
insert_isolation_cell
insert_level_shifters
insert_metal_filler
insert_ng_filler
insert_pad_filler
insert_port_protection_diodes
insert_redundant_vias
insert_spare_cells
insert_stdcell_filler
insert_tap_cells_by_rules
insert_well_filler
insert_zrt_redundant_vias
interp
is_false
is_true
is_zrt_routed_design
join
lappend
legalize_fp_placement
legalize_placement
lib2saif
license_users
lindex
link
link_physical_library
linsert
list
list_attributes
list_designs
list_drc_error_types
list_files
list_floorplan_data
list_instances
list_libs
list_licenses
list_mw_cels
list_partition_data
llength
lminus
load_fp_rail_map
load_of
load_upf
lrange
lreplace
ls
lsearch
lset
lsort
magnet_placement
man
map_freeze_silicon
map_isolation_cell
map_level_shifter_cell
map_power_switch
map_retention_cell
mark_clock_tree
mem
merge_clock_gates
merge_flip_chip_nets
merge_fp_hierarchy
merge_net_shapes
merge_saif
move_mw_cel_origin
move_objects
move_pins_on_edge
name_format
namespace
open
open_mw_cel
open_mw_lib
optimize_clock_tree
optimize_dft
optimize_flip_chip_route
optimize_fp_timing
optimize_netlist_hierarchy
optimize_power_switch
optimize_pre_cts_power
optimize_wire_via
order_rp_groups
pack_fp_macro_in_area
package
parse_proc_arguments
pid
place_flip_chip_array
place_flip_chip_ring
place_fp_pins
place_freeze_silicon
place_io_pads
place_opt
place_opt_feasibility
preroute_instances
preroute_standard_cells
print_message_info
print_proc_new_vars
print_suppressed_messages
printenv
printvar
proc
proc_args
proc_body
process_particle_probability_file
propagate_constraints
propagate_ilm
propagate_switching_activity
psynopt
push_down_fp_objects
push_flip_chip_route
push_up_fp_objects
puts
pwd
query_objects
quit
quit!
read
read_antenna_violation
read_aocvm
read_ddc
read_def
read_drc_error_file
read_file
read_flip_chip_bumps
read_floorplan
read_io_constraints
read_lib
read_mw_eco_list
read_parasitics
read_partition
read_rail_maps
read_saif
read_sdc
read_sdf
read_tdf_ports
read_verilog
read_zrt_route_guidance
rebuild_mw_lib
recompute_fit_bbox
recover_tie_connection
redirect
redo
reduce_fp_rail_stacked_via
refine_fp_macro_channels
refine_placement
regexp
regsub
remove_all_spacing_rules
remove_annotated_check
remove_annotated_delay
remove_annotated_transition
remove_annotations
remove_antenna_rules
remove_aocvm
remove_attribute
remove_base_arrays
remove_bounds
remove_buffer
remove_buffer_tree
remove_bus
remove_case_analysis
remove_cell
remove_cell_degradation
remove_cell_sites
remove_cell_vt_type
remove_checkpoint_designs
remove_clock
remove_clock_gates
remove_clock_gating_check
remove_clock_groups
remove_clock_latency
remove_clock_mesh
remove_clock_sense
remove_clock_transition
remove_clock_tree
remove_clock_tree_exceptions
remove_clock_tree_options
remove_clock_uncertainty
remove_congestion_options
remove_cts_scenario
remove_dangling_wires
remove_data_check
remove_design
remove_diode
remove_disable_clock_gating_check
remove_disable_timing
remove_distributed_hosts
remove_distributed_route
remove_dont_touch_placement
remove_dp_int_round
remove_drc_error
remove_driving_cell
remove_edit_groups
remove_fanout_load
remove_filler_with_violation
remove_flip_chip_route
remove_fp_block_shielding
remove_fp_feedthroughs
remove_fp_pin_constraints
remove_fp_pin_overlaps
remove_fp_plan_group_padding
remove_fp_rail_stacked_via
remove_fp_rail_voltage_area_constraints
remove_fp_relative_location
remove_fp_virtual_pad
remove_fp_voltage_area_constraints
remove_from_collection
remove_from_rp_group
remove_generated_clock
remove_host_options
remove_ideal_latency
remove_ideal_net
remove_ideal_network
remove_ideal_transition
remove_ignore_cell_timing
remove_ignored_layers
remove_input_delay
remove_io_antenna_properties
remove_io_constraints
remove_io_pin_overlap
remove_isolate_ports
remove_isolation_cell
remove_keepout_margin
remove_left_right_filler_rule
remove_level_shifters
remove_license
remove_map_power_switch
remove_mim_property
remove_mw_cel
remove_net
remove_net_routing
remove_net_routing_layer_constraints
remove_net_shape
remove_net_timing_spacing
remove_objects
remove_output_delay
remove_partition
remove_pg_network
remove_physical_bus
remove_pin_guides
remove_pin_name_synonym
remove_placement
remove_placement_blockage
remove_plan_groups
remove_pnet_options
remove_port
remove_power_domain
remove_power_switch
remove_preferred_routing_direction
remove_propagated_clock
remove_qor_snapshot
remove_rail_maps
remove_route_by_type
remove_route_guide
remove_routing_blockage
remove_routing_rules
remove_row_type
remove_rp_group_options
remove_rp_groups
remove_scaling_lib_group
remove_scan_def
remove_scan_pin_type
remove_scenario
remove_sdc
remove_site_row
remove_skew_group
remove_stdcell_filler
remove_supply_net
remove_supply_port
remove_target_library_subset
remove_terminal
remove_text
remove_tie_cells
remove_track
remove_unconnected_ports
remove_user_shape
remove_via
remove_voltage_area
remove_vt_filler_rule
remove_well_filler
remove_xtalk_prop
remove_zrt_filler_with_violation
remove_zrt_redundant_shapes
rename
rename_mw_cel
rename_mw_lib
replace_power_switch
report_adjusted_endpoints
report_ahfs_options
report_annotated_check
report_annotated_delay
report_annotated_transition
report_antenna_ratio
report_antenna_rules
report_aocvm
report_app_var
report_area
report_area_recovery_options
report_attribute
report_bounds
report_buffer_tree
report_buffer_tree_qor
report_bus
report_case_analysis
report_cbt_options
report_cell
report_cell_physical
report_cell_vt_type
report_change_list
report_check_library_options
report_checkpoint_designs
report_clock
report_clock_gating
report_clock_gating_check
report_clock_timing
report_clock_tree
report_clock_tree_optimization_options
report_clock_tree_power
report_congestion
report_congestion_options
report_constraint
report_critical_area
report_crpr
report_cts_batch_mode
report_delay_calculation
report_delay_estimation_options
report_design
report_design_lib
report_design_physical
report_direct_power_rail_tie
report_disable_timing
report_distributed_hosts
report_distributed_route
report_drc_error_type
report_droute_options
report_eco_history
report_edit_groups
report_error_coordinates
report_extraction_options
report_fast_mode
report_feasibility_options
report_filler_placement
report_flip_chip_bump_attributes
report_flip_chip_driver_bump
report_flip_chip_type
report_floorplan_data
report_fp_clock_plan_options
report_fp_macro_array
report_fp_macro_options
report_fp_pin_constraints
report_fp_placement
report_fp_placement_strategy
report_fp_rail_constraints
report_fp_rail_strategy
report_fp_rail_voltage_area_constraints
report_fp_relative_location
report_fp_shaping_strategy
report_fp_voltage_area_constraints
report_groute_options
report_hierarchy
report_host_options
report_ideal_network
report_ignored_layers
report_ilm
report_interclock_relation
report_internal_loads
report_io_antenna_properties
report_io_constraints
report_isolate_ports
report_isolated_via
report_isolation_cell
report_keepout_margin
report_latency_adjustment_options
report_lcc_hotspot
report_left_right_filler_rule
report_level_shifter
report_lib
report_milkyway_version
report_mim
report_mode
report_mpc_macro_array
report_mpc_macro_options
report_mpc_options
report_mpc_pnet_options
report_mpc_port_options
report_mpc_rectilinear_outline
report_mpc_ring_options
report_mtcmos_pna_strategy
report_mw_design_ecos
report_mw_lib
report_name_rules
report_names
report_net
report_net_changes
report_net_characteristics
report_net_delta_delay
report_net_fanout
report_net_routing_layer_constraints
report_net_routing_rules
report_noise
report_noise_calculation
report_operating_conditions
report_optimize_dft_options
report_optimize_pre_cts_power_options
report_parameter
report_path_group
report_pg_net
report_physical_bus
report_physical_signoff_options
report_pin_guides
report_pin_name_synonym
report_pin_shape
report_placement_utilization
report_pnet_options
report_port
report_port_protection_diodes
report_power
report_power_calculation
report_power_domain
report_power_gating
report_power_guide
report_power_options
report_power_pin_info
report_power_switch
report_preferred_routing_direction
report_preroute_drc_strategy
report_primetime_options
report_pst
report_qor
report_qor_snapshot
report_qtm_model
report_rail_options
report_reference
report_retention_cell
report_route_opt_strategy
report_route_options
report_route_zrt_common_options
report_route_zrt_detail_options
report_route_zrt_global_options
report_route_zrt_track_options
report_routing_rules
report_rp_group_options
report_saif
report_scan_chain
report_scenario_options
report_scenarios
report_si_options
report_signal_em
report_skew_group
report_spacing_rules
report_split_clock_gates_options
report_starrcxt_options
report_supply_net
report_supply_port
report_target_library_subset
report_threshold_voltage_group
report_tie_nets
report_timing
report_timing_derate
report_timing_requirements
report_tlu_plus_files
report_track
report_transitive_fanin
report_transitive_fanout
report_units
report_voltage_area
report_vt_filler_rule
report_write_stream_options
report_xtalk_route_options
report_zrt_net_properties
reset_clock_tree_optimization_options
reset_clock_tree_options
reset_clock_tree_references
reset_cts_batch_mode
reset_design
reset_fp_clock_plan_options
reset_latency_adjustment_options
reset_mode
reset_path
reset_split_clock_gates_options
reset_switching_activity
reset_timing_derate
reset_upf
resize_objects
resize_polygon
restore_design_settings
return
rotate_objects
route_area
route_auto
route_detail
route_differential
route_eco
route_flip_chip
route_fp_proto
route_global
route_group
route_htree
route_mesh_net
route_opt
route_rc_reduction
route_search_repair
route_spreadwires
route_track
route_widen_wire
route_zrt_auto
route_zrt_clock_tree
route_zrt_detail
route_zrt_eco
route_zrt_global
route_zrt_group
route_zrt_track
route_zrt_with_route_guidance
rp_group_inclusions
rp_group_instantiations
rp_group_references
run_parallel_jobs
run_signoff
save_design_settings
save_mw_cel
save_qtm_model
save_upf
scan
seek
select_mim_master_instance
send_flow_status
set
set_active_scenarios
set_ahfs_options
set_always_on_cell
set_always_on_strategy
set_annotated_check
set_annotated_delay
set_annotated_transition
set_aocvm_coefficient
set_app_var
set_area_recovery_options
set_attribute
set_auto_disable_drc_nets
set_buffer_opt_strategy
set_case_analysis
set_cbt_options
set_cell_degradation
set_cell_internal_power
set_cell_location
set_cell_row_type
set_cell_type
set_cell_vt_type
set_check_library_options
set_checkpoint_strategy
set_child_terminal
set_chiplevel_pad_physical_constraints
set_cle_options
set_clock_gating_check
set_clock_gating_registers
set_clock_groups
set_clock_latency
set_clock_sense
set_clock_transition
set_clock_tree_exceptions
set_clock_tree_optimization_options
set_clock_tree_options
set_clock_tree_references
set_clock_uncertainty
set_combinational_type
set_congestion_options
set_connection_class
set_context_margin
set_cost_priority
set_critical_range
set_cts_batch_mode
set_cts_scenario
set_current_command_mode
set_data_check
set_default_drive
set_default_driving_cell
set_default_fanout_load
set_default_input_delay
set_default_load
set_default_output_delay
set_delay_calculation
set_delay_estimation_options
set_design_license
set_design_top
set_die_area
set_direct_power_rail_tie
set_disable_clock_gating_check
set_disable_timing
set_distributed_route
set_domain_supply_net
set_dont_touch
set_dont_touch_network
set_dont_touch_placement
set_dont_use
set_dp_int_round
set_drive
set_driving_cell
set_droute_options
set_equal
set_error_view_property
set_extraction_options
set_false_path
set_fanout_load
set_fast_mode
set_feasibility_options
set_fix_hold
set_fix_hold_options
set_fix_multiple_port_nets
set_flip_chip_bump_attributes
set_flip_chip_cell_site
set_flip_chip_driver_array
set_flip_chip_driver_island
set_flip_chip_driver_ring
set_flip_chip_grid
set_flip_chip_options
set_flip_chip_type
set_fp_base_gate
set_fp_black_boxes_estimated
set_fp_black_boxes_unestimated
set_fp_block_ring_constraints
set_fp_clock_plan_options
set_fp_flow_strategy
set_fp_macro_array
set_fp_macro_options
set_fp_pin_constraints
set_fp_placement_strategy
set_fp_power_pad_constraints
set_fp_rail_constraints
set_fp_rail_region_constraints
set_fp_rail_strategy
set_fp_rail_voltage_area_constraints
set_fp_relative_location
set_fp_shaping_strategy
set_fp_trace_mode
set_fp_voltage_area_constraints
set_groute_options
set_hierarchy_color
set_host_options
set_ideal_latency
set_ideal_net
set_ideal_network
set_ideal_transition
set_ignore_cell_timing
set_ignored_layers
set_input_delay
set_input_transition
set_inter_clock_delay_options
set_isolate_ports
set_isolation
set_isolation_cell
set_isolation_control
set_keepout_margin
set_latency_adjustment_options
set_left_right_filler_rule
set_level_shifter
set_level_shifter_cell
set_level_shifter_strategy
set_level_shifter_threshold
set_lib_attribute
set_lib_cell_spacing_label
set_load
set_local_link_library
set_logic_dc
set_logic_one
set_logic_zero
set_macro_cell_bound_spot
set_max_area
set_max_capacitance
set_max_delay
set_max_dynamic_power
set_max_fanout
set_max_leakage_power
set_max_lvth_percentage
set_max_net_length
set_max_time_borrow
set_max_total_power
set_max_transition
set_mcmm_job_options
set_message_info
set_min_capacitance
set_min_delay
set_min_library
set_mode
set_mpc_macro_array
set_mpc_macro_options
set_mpc_options
set_mpc_pnet_options
set_mpc_port_options
set_mpc_rectilinear_outline
set_mpc_ring_options
set_mtcmos_pna_strategy
set_multicycle_path
set_mw_lib_reference
set_mw_technology_file
set_name
set_net_aggressors
set_net_routing_layer_constraints
set_net_routing_rule
set_object_boundary
set_object_fixed_edit
set_object_shape
set_object_snap_type
set_operand_isolation_scope
set_operating_conditions
set_opposite
set_optimize_dft_options
set_optimize_pre_cts_power_options
set_output_delay
set_pad_physical_constraints
set_parameter
set_partition_data
set_pg_pin_model
set_physical_signoff_options
set_physopt_cpulimit_options
set_pin_model
set_pin_name_synonym
set_pin_physical_constraints
set_place_opt_cts_strategy
set_pnet_options
set_port_fanout_number
set_port_location
set_power_guide
set_power_net_to_voltage_area
set_power_options
set_power_switch_cell
set_prefer
set_preferred_routing_direction
set_preroute_advanced_via_rule
set_preroute_drc_strategy
set_preroute_special_rules
set_primetime_options
set_propagated_clock
set_pulse_clock_cell
set_qtm_global_parameter
set_qtm_port_drive
set_qtm_port_load
set_qtm_technology
set_rail_options
set_register_type
set_related_supply_net
set_resistance
set_retention
set_retention_cell
set_retention_control
set_route_flip_chip_options
set_route_mode_options
set_route_opt_strategy
set_route_options
set_route_type
set_route_zrt_common_options
set_route_zrt_detail_options
set_route_zrt_global_options
set_route_zrt_track_options
set_row_type
set_rp_group_options
set_scaling_lib_group
set_scan_pin_type
set_scenario_options
set_scope
set_si_options
set_size_only
set_skew_group
set_spacing_label_rule
set_split_clock_gates_options
set_starrcxt_options
set_switching_activity
set_synlib_dont_get_license
set_target_library_subset
set_timing_derate
set_timing_ranges
set_tlu_plus_files
set_true_delay_case_analysis
set_unconnected
set_undoable_attribute
set_ungroup
set_unix_variable
set_user_grid
set_via_array_size
set_voltage
set_voltage_model
set_vt_filler_rule
set_write_stream_options
set_xtalk_route_options
set_zero_interconnect_delay_mode
set_zrt_net_properties
setenv
sh
sh_list_key_bindings
shape_fp_blocks
shell_is_in_upf_mode
signoff_drc
signoff_metal_fill
signoff_opt
size_cell
sizeof_collection
skew_opt
slot_wire
snap_objects
socket
sort_collection
sort_fp_pins
source
split
split_clock_gates
split_clock_net
split_mw_lib
split_net
split_objects
spread_spare_cells
spread_zrt_wires
start_gui
stop_gui
stretch_wire
string
sub_designs_of
sub_instances_of
subst
suppress_message
swap_cell_locations
switch
syntax_check
synthesize_fp_rail
tell
time
trace
trace_scan_chain
translate_zrt_parameters
trim_fill_eco
unalias
uncommit_fp_soft_macros
undefine_bus
undo
undo_config
undo_mark
ungroup
uniquify
uniquify_fp_mw_cel
unset
unset_hierarchy_color
unset_power_guide
unsuppress_message
update
update_bounds
update_clock_latency
update_flip_chip_pin_locations
update_lib
update_lib_model
update_lib_pg_pin_model
update_lib_pin_model
update_lib_voltage_model
update_physical_bus
update_timing
update_voltage_area
uplevel
upvar
variable
verify_drc
verify_lvs
verify_pg_nets
verify_route
verify_zrt_route
vwait
which
while
widen_zrt_wires
win_select_objects
win_set_filter
win_set_select_class
window_stretch
write
write_app_var
write_def
write_design_lib_paths
write_design_settings
write_environment
write_flip_chip_bumps
write_flip_chip_nets
write_floorplan
write_interface_timing
write_io_constraints
write_lib
write_lib_specification_model
write_link_library
write_mw_lib_files
write_parasitics
write_physical_constraints
write_physical_script
write_plib
write_qtm_model
write_route
write_rp_groups
write_saif
write_script
write_sdc
write_sdf
write_stream
write_verilog


#variables
HIERARCHY_DELIMITER
_Variable_Groups
__err
access_internal_pins
alib_library_analysis_path
allow_input_delay_min_greater_than_max
annotation_control
arch
atpg_bidirect_output_only
auto_attr_spread_debug
auto_index
auto_insert_level_shifters
auto_insert_level_shifters_on_clocks
auto_link_disable
auto_link_options
auto_noexec
auto_oldpath
auto_path
auto_ungroup_preserve_constraints
auto_wire_load_selection
bin_path
bind_unused_hierarchical_pins
bpv_skip_designrulewidth_spacing_syntax
budget_generate_critical_range
budget_map_clock_gating_cells
budgeting_allow_negative_delays
budgeting_enable_hier_si
bus_inference_descending_sort
bus_inference_style
bus_minus_style
bus_multiple_separator_style
bus_naming_style
bus_range_separator_style
cache_dir_chmod_octal
cache_file_chmod_octal
case_analysis_log_file
case_analysis_propagate_through_icg
case_analysis_with_logic_constants
ccl_enable_always
change_names_bit_blast_negative_index
change_names_dont_change_bus_members
change_selection_no_coreARGS
change_selection_too_many_objectsARGS
check_design_allow_non_tri_drivers_on_tri_bus
check_design_allow_unknown_wired_logic_type
check_error_list
cmd
cmds
collection_deletion_effort
collection_result_display_limit
command_log_file
company
compatibility_version
compile_clock_gating_through_hierarchy
compile_dont_use_dedicated_scanout
compile_instance_name_prefix
compile_instance_name_suffix
compile_keep_original_for_external_references
compile_log_format
compile_power_domain_boundary_optimization
compile_retime_exception_registers
compile_seqmap_identify_shift_registers
compile_seqmap_identify_shift_registers_with_synchronous_logic
compile_ultra_ungroup_small_hierarchies
compile_use_fast_delay_mode
complete_mixed_mode_extraction
context_check_status
copy_metal_blockage_to_fram_view
cp_full_abut_cts_region_aware
cp_in_full_abut_mode
cp_para_max_subjob_num
create_clock_no_input_delay
ctldb_use_old_prot_flow
cts_add_clock_domain_name
cts_blockage_aware
cts_clock_opt_batch_mode
cts_clock_source_is_exclude_pin
cts_do_characterization
cts_enable_clock_at_hierarchical_pin
cts_enable_rc_constraints
cts_fix_clock_tree_sinks
cts_fix_drc_beyond_exceptions
cts_force_ilm_keep_full_clock_tree
cts_force_user_constraints
cts_instance_name_prefix
cts_move_clock_gate
cts_net_name_prefix
cts_prects_upsize_gates
cts_push_down_buffer
cts_rc_relax_factor
cts_region_aware
cts_target_cap
cts_target_transition
cts_traverse_dont_touch_subtrees
cts_use_debug_mode
cts_use_lib_max_fanout
cts_use_sdc_max_fanout
current_design
current_instance
date_time
db_load_ccs_data
db_load_ccs_noise_data
db_load_ccs_power_data
dc_lib_project_enabled
dcod_disable_chgmgr_fine_grain_notification
dcod_disable_chgmgr_notification
dct_placement_ignore_scan
ddc_allow_unknown_packed_commands
ddc_verbose
default_input_delay
default_name_rules
default_output_delay
default_port_connection_class
default_schematic_options
disable_auto_time_borrow
disable_case_analysis
disable_delta_slew_for_tran_cstr
disable_library_transition_degradation
do_operand_isolation
dont_cut_non_pin_metal_as_pin
dont_touch_nets_with_size_only_cells
dont_trim_via_region_by_cell_boundary
droute_advRouteCompletionEffort
droute_advRouteLoop
droute_advancedRouteLoops
droute_areaSrLoop
droute_autoSaveInterval
droute_autoSrLoop
droute_checkFixedDRC
droute_connBrokenNet
droute_connTieOff
droute_connTieRail
droute_doMaxCapConx
droute_doMaxTransConx
droute_doProbeConx
droute_doSelectedNetAntennaConx
droute_doXtalkConx
droute_ecoListToFile
droute_ecoMode
droute_ecoScope
droute_ecoSrLoop
droute_enableFullSBExtLevel
droute_enable_one_pass_partitioning
droute_expandFillTracks
droute_fillDataType
droute_fillEndByMinSpcPercent
droute_fillMetalCloseToMinDensityValue
droute_fillMetalUniformly
droute_fillViaDataType
droute_fixIsoViaTouchClock
droute_fixIsoViaTouchPG
droute_fixMinEdgeLengthByFilling
droute_flccNoRollBack
droute_followPolyTrkForPolyFill
droute_groupSrLoop
droute_highEffortViaDoubling
droute_lowSkewClkRoute
droute_m10MacroDensity
droute_m11MacroDensity
droute_m12MacroDensity
droute_m13MacroDensity
droute_m14MacroDensity
droute_m15MacroDensity
droute_m1MacroDensity
droute_m1NoWrongWayExtraCost
droute_m2MacroDensity
droute_m3MacroDensity
droute_m4MacroDensity
droute_m5MacroDensity
droute_m6MacroDensity
droute_m7MacroDensity
droute_m8MacroDensity
droute_m9MacroDensity
droute_maxOffGridTrack
droute_maxTieOffDistance
droute_metalFillDensityIncrement
droute_minLengthCheckCutMode
droute_minShieldLength
droute_numCPUs
droute_offGridCost
droute_offsetFillTrack
droute_optDelaySlackTarget
droute_optDelaySrLoop
droute_optSetup
droute_optSrLoop
droute_optViaHoldTimeThreshold
droute_optViaReportExcludedNets
droute_optViaSetupSlackThreshold
droute_optViaSrLoop
droute_optViaTimingDriven
droute_optimizeRouteGroup
droute_parallelLengthMode
droute_pinTaperLengthLimit
droute_pinTaperMode
droute_polyMacroDensity
droute_polycontMacroDensity
droute_reduceFatExtensionRange
droute_reportLimit
droute_rerouteUserWire
droute_rerunDRC
droute_resetMinMaxLayer
droute_shieldAvoidFatViaArray
droute_shieldLimitSboxExt
droute_shieldRerouteSignalNets
droute_shieldSkipNotShieldedSboxes
droute_shieldTieAsShield
droute_shieldTieForce
droute_shieldViaMinSpacing
droute_smallJogMinLength
droute_srLoop
droute_stopIfNoLicense
droute_suppressIllegalContactMsg
droute_timeLimit
droute_timingDriven
droute_timingSpace
droute_treatTiedFillAsFillToFillSpacing
droute_trimUserAntenna
droute_ultraWideWireMode
droute_via10MacroDensity
droute_via11MacroDensity
droute_via12MacroDensity
droute_via13MacroDensity
droute_via14MacroDensity
droute_via1MacroDensity
droute_via2MacroDensity
droute_via3MacroDensity
droute_via4MacroDensity
droute_via5MacroDensity
droute_via6MacroDensity
droute_via7MacroDensity
droute_via8MacroDensity
droute_via9MacroDensity
droute_wireWidenForceWrongWay
droute_wireWidenIgnoreMinEdgeLengthVio
droute_wireWidenMinLength
droute_wireWidenPieceWise
droute_wireWidenSrLoop
droute_wireWidenTimingDriven
droute_wireWidenWidthScheme
droute_wrongWayExtraCost
duplicate_ports
echo_include_commands
eco_align_design_verbose
eco_allow_register_type_difference
eco_connect_resource_cell_inputs
eco_correspondence_analysis_verbose
eco_directives_verbose
eco_implement_effort_level
eco_instance_name_prefix
eco_recycle_verbose
eco_remap_register_verbose
eco_reuse_verbose
enable_auto_attr_spread
enable_bus_name_mapping
enable_cell_based_verilog_reader
enable_instances_in_report_net
enable_lib_cell_case_sensitivity
enable_page_mode
enable_recovery_removal_arcs
enable_slew_degradation
enable_special_level_shifter_naming
enable_verilog_netlist_reader
enlarge_45degree_geometry_sliced_value
err
estimate_io_latency
estimate_resource_preference
exit_delete_command_log_file
exit_delete_filename_log_file
external_pin_file
filename_log_file
find_allow_only_non_hier_ports
find_converts_name_lists
find_ignore_case
focalopt_endpoint_margin
font_library
fp_allocate_mcmm_script_dir
fp_bb_flow
fp_snap_type
fsm_auto_inferring
fsm_enable_state_minimization
fsm_export_formality_state_info
gen_bussing_exact_implicit
gen_cell_pin_name_separator
gen_create_netlist_busses
gen_dont_show_single_bit_busses
gen_match_ripper_wire_widths
gen_max_compound_name_length
gen_max_ports_on_symbol_side
gen_open_name_postfix
gen_open_name_prefix
gen_show_created_busses
gen_show_created_symbols
gen_single_osc_per_name
generate_via_region_when_pin_width_all_less_than_via_width
generic_symbol_library
ggui_use_mw_collections
groute_VABoundaryToLSWeight
groute_avoidCouplingUser
groute_avoidXtalk
groute_blncdToSkewCntrlRatio
groute_blockEdgeAccess
groute_brokenNetsThresholdPercent
groute_clockBalanced
groute_clockComb
groute_combDistance
groute_combMaxConnections
groute_compactMode
groute_congestionWeight
groute_densityDriven
groute_detourLimitMinNetLen
groute_extraCostsApplyPercent
groute_extraWireLengthOpt
groute_forceUpperLayersForCritNets
groute_horReserveTracks
groute_ignoreViaBlockage
groute_incremental
groute_macroBndryDir
groute_macroBndryExt
groute_macroBndryTrkUtil
groute_macroBndryWidth
groute_macroCornerTrkUtil
groute_mapOnly
groute_maxDetourPercent
groute_netCriticality
groute_noTopLevelBusFeedThroughs
groute_numXtalkWindow
groute_paEqPinNetMaxPort
groute_powerDriven
groute_rcOptByLength
groute_reportDemandOnly
groute_reportEffectiveOverflow
groute_reportGCellDensity
groute_reportNetOrdering
groute_reserveTracksForPowerFile
groute_skewControl
groute_skewControlNetBBLowBound
groute_skewControlWeight
groute_speed
groute_timingDriven
groute_timingWeight
groute_turboMode
groute_verReserveTracks
groute_xtalkWeight
gui_auto_start
gui_custom_setup_files
gui_default_window_type
gui_disable_custom_setup
gui_online_browser
hdlin_auto_save_templates
hdlin_enable_assertions
hdlin_enable_elaborate_ref_linking
hdlin_mux_size_only
hdlin_optimize_pla_effort
hdlin_reporting_level
hdlin_sv_ieee_assignment_patterns
hdlin_sv_packages
hercules_home_dir
hier_dont_trace_ungroup
high_fanout_net_pin_capacitance
high_fanout_net_threshold
host_core
host_cpu
host_file
host_mem
host_model
host_name
icc_magnetpl_stop_after_seq_cell
icc_snapshot_storage_location
icv_home_dir
ignoreStackViaOnPG
ignore_binding_open_pins
ignore_guardband
ilm_enable_power_calculation
ilm_ignore_percentage
ilm_preserve_core_constraints
in_gui_session
infer_name_hierarchy
inherit_parent_dont_touch
init_path
initial_target_library
insert_dft_clean_up
insert_test_design_naming_style
lbo_cells_in_regions
lc
ldd_return_val
level_shifter_naming_prefix
lib_thresholds_per_lib
lib_use_thresholds_per_pin
libgen_max_differences
libsetup_macro_opcond_inference_level
libsetup_match_pt_for_macro_pad
libsetup_max_auto_opcond_message
libsetup_pad_opcond_inference_level
libsetup_switch_opcond_inference_level
link_force_case
link_library
link_path
ltl_obstruction_type
magnet_placement_disable_overlap
magnet_placement_fanout_limit
mcmm_enable_high_capacity_flow
mcmm_high_capacity_effort_level
monitor_cpu_memory
motif_files
mpc_disable_macro_fitting
mpc_disable_pad_legalization
mpc_dont_cut_pnet_over_macros
multi_pass_test_generation
mux_auto_inferring_effort
mv_allow_ls_on_leaf_pin_boundary
mv_size_only_level_shifters
mv_use_std_cell_for_isolation
mw_allow_rect_and_polygon_in_def
mw_attr_value_extra_braces
mw_attr_value_no_space
mw_cel_as_escaped
mw_cell_name
mw_create_netlist_from_CEL
mw_current_design
mw_design_library
mw_disable_escape_char
mw_enable_net_bus
mw_ground_port
mw_hdl_bus_dir_for_undef_cell
mw_hdl_expand_cell_with_no_instance
mw_hdl_stop_at_FRAM_cells
mw_hdl_top_module_list
mw_logic0_net
mw_logic1_net
mw_open_design_with_gui
mw_pgconn_cell_inst
mw_pgconn_cell_master
mw_power_port
mw_read_ignore_corner_cell
mw_read_ignore_filler_cell
mw_read_ignore_pad_cell
mw_read_ignore_unconnected_cell
mw_reference_library
mw_site_name_mapping
mw_use_pdb_lib_format
mwdc_allow_higher_mem_usage
new_idn_switch
no_routing_blockage_output_on_masks
open_soft_macro_push_down_shapes
optimize_reg_always_insert_sequential
optimize_reg_max_time_borrow
optimize_reg_retime_clock_gating_latches
physopt_area_critical_range
physopt_cell_count_threshold
physopt_change_list
physopt_check_site_array_overlap
physopt_checkpoint_stage
physopt_cpu_limit
physopt_create_missing_physical_libcells
physopt_delete_unloaded_cells
physopt_dw_opto
physopt_enable_extractor_rc
physopt_enable_power_optimization
physopt_enable_router_process
physopt_enable_rp_in_xg_mode
physopt_enable_tlu_plus
physopt_enable_tlu_plus_process
physopt_enable_via_res_support
physopt_hard_keepout_distance
physopt_heterogeneous_site_array
physopt_ignore_lpin_fanout
physopt_ignore_structure
physopt_macro_cell_height_threshold
physopt_mw_checkpoint_filename
physopt_new_fix_constants
physopt_pin_based_pad
physopt_power_critical_range
physopt_ref_pdef_loaded
physopt_row_overlap_threshold
physopt_rp_enable_orient_opt
physopt_spatial_constraint_lists
physopt_tie_const_cells
physopt_tie_spare_cells
physopt_ultra_high_area_effort
placer_disable_auto_bound_for_gated_clock
placer_disable_macro_placement_timeout
placer_dont_error_out_on_conflicting_bounds
placer_enable_enhanced_router
placer_gated_register_area_multiplier
placer_max_cell_density_threshold
placer_run_in_separate_process
placer_soft_keepout_channel_width
port_complement_naming_style
power_cg_all_registers
power_cg_auto_identify
power_cg_balance_stages
power_cg_cell_naming_style
power_cg_derive_related_clock
power_cg_designware
power_cg_enable_alternative_algorithm
power_cg_ext_feedback_loop
power_cg_flatten
power_cg_gated_clock_net_naming_style
power_cg_ignore_setup_condition
power_cg_inherit_timing_exceptions
power_cg_module_naming_style
power_cg_print_enable_conditions
power_cg_print_enable_conditions_max_terms
power_cg_reconfig_stages
power_default_static_probability
power_default_toggle_rate
power_default_toggle_rate_type
power_do_not_size_icg_cells
power_driven_clock_gating
power_enable_one_pass_power_gating
power_enable_power_gating
power_fix_sdpd_annotation
power_fix_sdpd_annotation_verbose
power_hdlc_do_not_split_cg_cells
power_keep_license_after_power_commands
power_lib2saif_rise_fall_pd
power_min_internal_power_threshold
power_model_preference
power_opto_extra_high_dynamic_power_effort
power_preserve_rtl_hier_names
power_rclock_inputs_use_clocks_fanout
power_rclock_unrelated_use_fastest
power_rclock_use_asynch_inputs
power_remove_redundant_clock_gates
power_rtl_saif_file
power_sa_propagation_effort
power_sa_propagation_verbose
power_same_switching_activity_on_connected_objects
power_sdpd_message_tolerance
power_sdpd_saif_file
precise_cut_metal_blockage
preroute_AlignRailsEnds
preroute_ContactSizeSelection
preroute_DropViasToLargeAreaFirst
preroute_GcrEnable
preroute_SetDrcMenuFatBlockagesDefault
preroute_SetDrcMenuFatViaDefault
preroute_SetDrcMenuProtectAccessEdge
preroute_SetViaShare
preroute_StackingViaMaxNumberOfCut
preroute_TreatMaxNumRowsAsExactNumRows
preroute_UseCutLayerRule4ViaPair
preroute_UseFatContactIfBothWiresFat
preroute_advancedViasOnly
preroute_checkDRCforRailPins
preroute_cutStdRowsByPlacementBlockages
preroute_layerSwitching
preroute_regressionMode
preroute_rotateMinAreaStubOverRails
preroute_rotateViasToMaximizeCutsCount
preroute_trimWiresByViaCovers
preroute_tryOtherDirectionsIfFails
preroute_viaTargetWidthThreshold
product_build_date
product_version
psyn_ignore_bounds
psyn_ignore_mobility
psyn_onroute_disable_cap_drc
psyn_onroute_disable_fanout_drc
psyn_onroute_disable_hold_fix
psyn_onroute_disable_netlength_drc
psyn_onroute_disable_trans_drc
psyn_stress_map
psynopt_high_fanout_legality_limit
rc_degrade_min_slew_when_rd_less_than_rnet
rc_driver_model_mode
rc_input_threshold_pct_fall
rc_input_threshold_pct_rise
rc_noise_model_mode
rc_output_threshold_pct_fall
rc_output_threshold_pct_rise
rc_receiver_model_mode
rc_slew_derate_from_library
rc_slew_lower_threshold_pct_fall
rc_slew_lower_threshold_pct_rise
rc_slew_upper_threshold_pct_fall
rc_slew_upper_threshold_pct_rise
read_db_lib_warnings
read_translate_msff
register_duplicate
register_replication_naming_style
remove_route_guide_on_fat_pin
reoptimize_design_changed_list_file_name
report_default_significant_digits
represent_power_ground_pins_by_vertical_sliced_rectangles
rom_auto_inferring
route_doubleViaDriven
route_layerExtraCostByRC
route_m10ExtraCost
route_m10Freeze
route_m11ExtraCost
route_m11Freeze
route_m12ExtraCost
route_m12Freeze
route_m13ExtraCost
route_m13Freeze
route_m14ExtraCost
route_m14Freeze
route_m15ExtraCost
route_m15Freeze
route_m1ExtraCost
route_m1Freeze
route_m2ExtraCost
route_m2Freeze
route_m3ExtraCost
route_m3Freeze
route_m4ExtraCost
route_m4Freeze
route_m5ExtraCost
route_m5Freeze
route_m6ExtraCost
route_m6Freeze
route_m7ExtraCost
route_m7Freeze
route_m8ExtraCost
route_m8Freeze
route_m9ExtraCost
route_m9Freeze
route_noVoltAreaFeedThru
route_polyContExtraCost
route_polyExtraCost
route_polyFreeze
route_splitTimer
route_via10ExtraCost
route_via11ExtraCost
route_via12ExtraCost
route_via13ExtraCost
route_via1ExtraCost
route_via2ExtraCost
route_via3ExtraCost
route_via4ExtraCost
route_via5ExtraCost
route_via6ExtraCost
route_via7ExtraCost
route_via8ExtraCost
route_via9ExtraCost
route_viaFreeze
routeopt_allow_min_buffer_with_size_only
routeopt_checkpoint
routeopt_density_limit
routeopt_disable_cpulimit
routeopt_drc_over_timing
routeopt_preserve_routes
routeopt_skip_report_qor
routeopt_xtalk_reduction_setup_threshold
rp_shift_column_for_fixed_cells
sdc_version
sdc_write_unambiguous_names
sdf_enable_cond_start_end
sdfout_allow_non_positive_constraints
sdfout_min_fall_cell_delay
sdfout_min_fall_net_delay
sdfout_min_rise_cell_delay
sdfout_min_rise_net_delay
sdfout_time_scale
sdfout_top_instance_name
sdfout_write_to_output
search_path
set_isolate_ports
sh_allow_tcl_with_set_app_var
sh_allow_tcl_with_set_app_var_no_message_list
sh_arch
sh_command_abbrev_mode
sh_command_log_file
sh_continue_on_error
sh_dev_null
sh_enable_line_editing
sh_enable_page_mode
sh_enable_stdout_redirect
sh_line_editing_mode
sh_new_variable_message
sh_new_variable_message_in_proc
sh_new_variable_message_in_script
sh_output_log_file
sh_product_version
sh_script_stop_severity
sh_source_emits_line_numbers
sh_source_logging
sh_source_uses_search_path
sh_tcllib_app_dirname
sh_user_man_path
sheet_sizes
si_filter_accum_aggr_noise_peak_ratio
si_filter_per_aggr_noise_peak_ratio
si_use_partial_grounding_for_min_analysis
si_xtalk_reselect_delta_and_slack
si_xtalk_reselect_delta_delay
si_xtalk_reselect_delta_delay_ratio
si_xtalk_reselect_max_mode_slack
si_xtalk_reselect_min_mode_slack
signoff_enable_dmsa_fix_hold
signoff_enable_dmsa_fix_signoff
signoff_pt_dmsa_script_file
single_group_per_sheet
site_info_file
skew_opt_skip_clock_balancing
skew_opt_skip_ideal_clocks
skew_opt_skip_propagated_clocks
slice_signal_pin_vertically
sort_outputs
spatial_constraint_lists
suppress_errors
symbol_library
synopsys_exec
synopsys_program_name
synopsys_root
syntax_check_status
synthesized_clocks
synthetic_library
systemcout_debug_mode
systemcout_levelize
target_library
tcl_interactive
tcl_library
tcl_patchLevel
tcl_pkgPath
tcl_platform
tcl_version
template_naming_style
template_parameter_style
template_separator_style
tested_technology
testsim_print_stats_file
text_editor_command
text_print_command
text_unselect_on_button_press
timing_aocvm_enable_analysis
timing_ccs_load_on_demand
timing_check_defaults
timing_clock_gating_propagate_enable
timing_clock_reconvergence_pessimism
timing_crpr_remove_clock_to_data_crp
timing_crpr_threshold_ps
timing_disable_cond_default_arcs
timing_edge_specific_source_latency
timing_enable_multiple_clocks_per_reg
timing_enable_non_sequential_checks
timing_gclock_source_network_num_master_registers
timing_input_port_clock_shift_one_cycle
timing_input_port_default_clock
timing_non_unate_clock_compatibility
timing_remove_clock_reconvergence_pessimism
timing_report_attributes
timing_self_loops_no_skew
timing_separate_clock_gating_group
timing_single_core
timing_use_clock_specific_transition
timing_use_driver_arc_transition_at_clock_source
timing_use_enhanced_capacitance_modeling
trackAssign_XTalkParam
trackAssign_densityDriven
trackAssign_evenSpaceAdjustment
trackAssign_extraViaGridCheck
trackAssign_m0LayerLengthLimit
trackAssign_m10LayerLengthLimit
trackAssign_m11LayerLengthLimit
trackAssign_m12LayerLengthLimit
trackAssign_m13LayerLengthLimit
trackAssign_m14LayerLengthLimit
trackAssign_m15LayerLengthLimit
trackAssign_m1LayerLengthLimit
trackAssign_m2LayerLengthLimit
trackAssign_m3LayerLengthLimit
trackAssign_m4LayerLengthLimit
trackAssign_m5LayerLengthLimit
trackAssign_m6LayerLengthLimit
trackAssign_m7LayerLengthLimit
trackAssign_m8LayerLengthLimit
trackAssign_m9LayerLengthLimit
trackAssign_minimizeJog
trackAssign_netLayerLengthLimit
trackAssign_noOffGridRouting
trackAssign_noiseThreshold
trackAssign_numCPUs
trackAssign_parallelLimit
trackAssign_parallelLimitMode
trackAssign_runTimeMode
trackAssign_runTimingMode
trackAssign_runXTalkIter
trackAssign_runXTalkMode
trackAssign_timingCost
trackAssign_tryGlobalLayerFirst
trackAssign_tryGlobalLayerOnly
trackAssign_variableWidthAdjustment
transfer_reserved_metalblockage_within_pin_to_viablockage
trim_via_region_by_top_bottom_cell_boundary
ungroup_keep_original_design
uniquify_keep_original_design
uniquify_naming_style
upf_charz_allow_port_punch
upf_extension
upf_levshi_on_constraint_only
upf_version
useAbstractClockSchematic
use_ccs_in_sdn
use_port_name_for_oscs
var_mux_mbm
verbose_messages
veriloglib_enable
veriloglib_sdf_edge
veriloglib_tb_compare
veriloglib_tb_x_eq_dontcare
veriloglib_write_recrem_as_setuphold
verilogout_equation
verilogout_higher_designs_first
verilogout_ignore_case
verilogout_include_files
verilogout_no_negative_index
verilogout_no_tri
verilogout_show_unconnected_pins
verilogout_single_bit
verilogout_unconnected_prefix
via_can_change_pin_shape
via_output_layers_same_as_input
via_region_honor_multiple_cut_rule
view_analyze_file_suffix
view_arch_types
view_background
view_busy_during_selection
view_cache_images
view_command_log_file
view_command_win_max_lines
view_dialogs_modal
view_disable_cursor_warping
view_disable_error_windows
view_disable_output
view_draw_text_breakpoint
view_error_window_count
view_execute_script_suffix
view_extend_thick_lines
view_icon_path
view_independent_dialogs
view_info_search_cmd
view_log_file
view_maximum_route_grids
view_on_line_doc_cmd
view_read_file_suffix
view_report_append
view_report_interactive
view_report_output2file
view_script_submenu_items
view_select_default_message
view_select_separator
view_set_cursor_area
view_set_selecting_color
view_tools_menu_items
view_use_integer_scaling
view_use_small_cursor
view_use_x_routines
view_watcher
view_write_file_suffix
when_analysis_permitted
when_analysis_without_case_analysis
win_select_objects_remove_adds_net_routing
write_name_nets_same_as_ports
write_sdc_output_lumped_net_capacitance
write_sdc_output_net_resistance
xt_filter_logic_constant_aggressors
