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        <dc:date>2011-04-29T08:05:30+00:00</dc:date>
        <title>IC Design Interview Question</title>
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        <description>IC Design Interview Question

	*  Inverter Layout
	*  Lays Macro Used

	*  Layout Interview Questions

	*  CMOS Circuits Design FAQ

	*  Place &amp; Route Question Set 1
	*  Interview Question Set 2</description>
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        <title>ASIC Backend Design</title>
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        <description>ASIC Backend Design

Flow Scripts

	*  Synopsys Implementation Tool Guide
	*  IC Compilier (ICC)
	*  PrimeTime
	*  Design Compiler(DC)
	*  RedHawk

	*  StarRC
	*  start

VLSI Basic Concept

	*  Unate
	*  Verilog
	*  FITS  Failures in Time

Models

	*  WLM - Wire load Model
	*  Extracted Timing Models (ETM)
	*  AOCV

EDA Tools

	*  SpyGlass

IC Design Interview Questoins

	*  IC Design Interview Question

VIM Setting

	*  VIM Setting For ICC

More VLSI

	*  For more VLSI information, please visit</description>
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