http://www.pythonclub.org/ 2026-07-13T01:18:20+00:00 http://www.pythonclub.org/ http://www.pythonclub.org/lib/tpl/dokuwiki/images/favicon.ico text/html 2011-10-27T03:22:56+00:00 http://www.pythonclub.org/vlsi/icc/def?rev=1319685776&do=diff Write Out DEF Files DEF & LEF For RedHawk write_def \ -compressed \ -routed_nets \ -rows_tracks_gcells \ -vias \ -all_vias \ -lef ${topLevel}.lef \ -regions_groups \ -components \ -pins \ -blockages \ -specialnets \ -nets \ -scanchain \ -output ${topLevel}.def.gz text/html 2011-07-12T04:12:37+00:00 http://www.pythonclub.org/vlsi/icc/dump-gif?rev=1310443957&do=diff ICC Dump Layout Window Snapshot proc dump_gif { filename } { gui_set_setting -window [gui_get_current_window -types Layout -mru] \ -setting viewshot -value ${filename}.bmp exec convert ${filename}.bmp ${filename}.gif file delete ${filename}.bmp } text/html 2012-01-10T06:48:58+00:00 http://www.pythonclub.org/vlsi/icc/floorplan-boundary?rev=1326178138&do=diff Floor Plan with Boundary Top set ignore_pad_height 1 create_boundary -coordinate {{0.000 0.000} {7800.000 7100.000}} initialize_floorplan \ -control boundary \ -row_core_ratio 1 \ -keep_io_place \ -left_io2core 0 \ -right_io2core 0 \ -bottom_io2core 0 \ -top_io2core 0 \ -start_first_row \ -keep_macro_place create_boundary -coordinate {{-24.000 -24.000} {7824.000 7124.000}} text/html 2011-09-30T08:15:05+00:00 http://www.pythonclub.org/vlsi/icc/flow?rev=1317370505&do=diff ICC Flow Scripts ICC Unitlity * ICC Dump Layout Window Snapshot Floorplan * RP scripts * Set Port Location Power Strap * Add Macro Placement & Route Blockage * Add Placement & Route Blockage to IO Cells * Create Route Guide Around Macro Blockage * Add Macro Placement & Route Blockage * Add Reverse Blockage Placement Write Out Files * Write Out DEF Files * Create Frame View text/html 2011-12-09T15:01:56+00:00 http://www.pythonclub.org/vlsi/icc/frame?rev=1323442916&do=diff Create Frame View create_macro_fram -library ${design_vars(mw_lib)} -cell_name ${design_vars(subblks_ics)} \ -routing_blockage_output_layer metBlk \ -extract_blockage_by_merge_with_threshold { \ m7 0 0 m8 0 0 m9 0 0} ########## make size clock ports tcl in fram/cell view ################### proc maketcl {} { global width global length set ports_file ./p.out set portslist [open $ports_file a+] foreach_in_collection sauce [filter_collection [get_attribute [get_clocks] sources -quiet] "obje… text/html 2011-04-20T06:20:59+00:00 http://www.pythonclub.org/vlsi/icc/io-blockage?rev=1303280459&do=diff Add Placement & Route Blockage to IO Cells Scripts ### NOTE : WARNING ### ### add_io_cover takes two arguments. The first is the hard blockage distance ### around the io. The second is the amount the PG route guide is INSET from ### that blockage -- a number picked to be slightly larger than half the standard ### cell PG rail width. The reason for the inset is to prevent a situation where ### placement rows wind up without a PG rail. ### d = blockage border [one row default], e is h… text/html 2011-04-20T06:24:34+00:00 http://www.pythonclub.org/vlsi/icc/macro-blockage?rev=1303280674&do=diff Add Macro Placement & Route Blockage Scripts ### NOTE : WARNING ### ### add_macro_cover takes two arguments. The first is the hard blockage distance ### around the macro. The second is the amount the PG route guide is INSET from ### that blockage -- a number picked to be slightly larger than half the standard ### cell PG rail width. The reason for the inset is to prevent a situation where ### placement rows wind up without a PG rail. ### d = blockage border [one row default], e is … text/html 2012-01-12T09:21:13+00:00 http://www.pythonclub.org/vlsi/icc/macro-list?rev=1326360073&do=diff Script to Get Macro List set all_memory [ all_macro_cells ] array set mem_count {} array set mem_area {} foreach_in_collection m $all_memory { set ref_name [ get_attr $m ref_name ] set mem_count($ref_name) 0 set mem_area($ref_name) [ get_attr $m area ] } foreach_in_collection m $all_memory { set ref_name [ get_attr $m ref_name ] set mem_count($ref_name) [expr $mem_count($ref_name) + 1] } foreach {ref_name count} [array get mem_count] { set area $mem_area($ref_name) echo $ref… text/html 2011-06-17T03:32:32+00:00 http://www.pythonclub.org/vlsi/icc/macro-side-routeguide?rev=1308281552&do=diff Create Route Guide Around Macro proc gdh_create_macro_side_route_guide {} { set all_macros [all_macro_cells] set n 0 set route_guide_prefix macro_side_route_guide_ remove_route_guide ${route_guide_prefix}* foreach_in_collection m $all_macros { set bbox [get_attribute $m bbox] set llx [ lindex $bbox 0 0 ] set lly [ lindex $bbox 0 1 ] set trx [ lindex $bbox 1 0 ] set try [ lindex $bbox 1 1 ] set route_guide_bbox_left "[expr $llx-5] $lly $llx $try" set ro… text/html 2011-11-30T06:44:08+00:00 http://www.pythonclub.org/vlsi/icc/port-location?rev=1322635448&do=diff Set Port Location Using ICC set_port_location proc place_ports_1 {} { set unplaced_ports [get_ports {*sms* LSI* *bist* }] set y_start [expr 14.995 + 0.36*2] set y $y_start set dy 0.36 foreach_in_collection port $unplaced_ports { set direction [get_attribute $port direction] set_port_location -coordinate "0 $y" -layer_name M5 -layer_area "0 $y 0.07 [expr $y + 0.07]" $port set_attribute $port direction $direction set y [expr $y + $dy] change_selection $port b… text/html 2012-03-07T13:07:37+00:00 http://www.pythonclub.org/vlsi/icc/qor-re-format?rev=1331125657&do=diff proc_qor Sourcing the attached proc_qor.tcl gives access to the following two procedures to generate and compare more readable QoR files than those produced by the report_qor command: proc_qor Reformats the output of the report_qor command. proc_compare_qor text/html 2014-08-26T08:16:34+00:00 http://www.pythonclub.org/vlsi/icc/report-track-utilization?rev=1409040994&do=diff Script to Report the Utilization of Each Metal Track in ICC Description To report the utilization of each track (how much of the track is filled with routes) in a specified metal layer, along with its starting coordinates, use the track_route_utilization_in_design Tcl procedure, which is defined in thetrack_route_util.tcl script. The starting location of a vertical track is calculated with respect to the lower design boundary. The starting location of a horizontal track is calculated with resp… text/html 2011-07-12T04:59:43+00:00 http://www.pythonclub.org/vlsi/icc/reverse-blockage?rev=1310446783&do=diff Add Reverse Blockage Add tap cell not support add to a specified area. As a wrok around, we can block all other area except the blockage. The following script is used to create reverse hard blockages. proc remove_reverse_hard_blockage { } { remove_placement_blockage tap_blockage_* } proc add_reverse_hard_blockage { llx lly rtx rty } { set core_bbox [ get_attribute [get_core_area] bbox ] set core_llx [ lindex $core_bbox 0 0 ] set core_lly [ lindex $core_bbox 0 1 ] set core_rtx [ li… text/html 2011-04-19T07:49:52+00:00 http://www.pythonclub.org/vlsi/icc/rp?rev=1303199392&do=diff RP scripts 根据相同的master创建RP proc create_macro_rp {} { set all_macros [get_cells -hierarchical -filter "mask_layout_type==macro"] set all_ref_names [] foreach_in_collection m $all_macros { set ref_name [get_attribute $m ref_name] if { [lsearch $all_ref_names $ref_name] == -1 } { lappend all_ref_names $ref_name } } echo $all_ref_names foreach ref_name $all_ref_names { set macros [get_cells -hierarchical -filter "ref_name==$ref_name"] set count [sizeof_collec… text/html 2014-09-02T07:56:20+00:00 http://www.pythonclub.org/vlsi/icc/script-highlight-clock-paths?rev=1409644580&do=diff Script to Highlight Launch and Capture Clock Paths in the Layout You can use the get_timing_paths command with the get_attribute command to create collections of the timing paths, and use the gui_change_highlight command to highlight each collection of paths with a unique color in the text/html 2010-08-17T17:42:57+00:00 http://www.pythonclub.org/vlsi/icc/show-clock-tree?rev=1282066977&do=diff Using Tcl Commands to Highlight Clock Trees in the Layout Window Question: How do I highlight clock trees in the IC Compiler layout window by using Tcl commands? Answer: In IC Compiler version 2008.09 or later, you can use the following commands to highlight clock trees in the layout window: text/html 2014-11-26T02:50:14+00:00 http://www.pythonclub.org/vlsi/icc/start?rev=1416970214&do=diff IC Compilier (ICC) ICC Unitlity * ICC Dump Layout Window Snapshot * proc_qor Floorplan * Floor Plan with Boundary * RP scripts * Set Port Location * Script to Get Macro List Power Strap * Add Macro Placement & Route Blockage * Add Placement & Route Blockage to IO Cells * Create Route Guide Around Macro Blockage * Add Macro Placement & Route Blockage * Add Reverse Blockage Placement CTS * Script to Highlight Launch and Capture Clock Paths in the Layout Route … text/html 2011-11-28T08:10:07+00:00 http://www.pythonclub.org/vlsi/icc/stream-out-gds2?rev=1322467807&do=diff Write GDSII set mw_design_lib my.mwlib set fs_release /tools/fip40.3/lsi40nm_3.0-current/tsmc_cln40g/ set streamout_mw_file $fs_release/shared/synopsys/icc_tech/lsi40_7+2.lmap_out set_write_stream_options \ -map_layer $streamout_mw_file \ -child_depth 10000 \ -output_filling [list fill] \ -output_outdated_fill \ -keep_data_type \ -allow_fill_data_mapping \ -output_pin [list text geometry] \ -output_net [list text plex] \ -output_geometry_property \ -compre… text/html 2010-06-21T05:05:36+00:00 http://www.pythonclub.org/vlsi/icc/variables?rev=1277096736&do=diff ICC Variables Placement legalize_support_phys_only_cell The check_legality command does have the capability to report overlapping between tap_cells and standard cells. This feature is OFF by default. To enable the feature and get the report, do the following: set legalize_support_phys_only_cell true check_legality -verbose text/html 2011-11-17T03:05:14+00:00 http://www.pythonclub.org/vlsi/icc/write-verilog-netlist?rev=1321499114&do=diff Write Verilog (Netlist) Net List with DeCAP for Power #in icc set force_cells [list DCAPNPNRTO10SXD DCAPNPNRTO9SXD DCAPNPNRTO8SXD DCAPNPNRTO7SXD DCAPNPNRTO6SXD DCAPNPNRTO5SXD DCAPNPNRTO4SXD DCAPNPNRTO3SXD] write_verilog -no_unconnected_cells -force_output_references $force_cells ./${topLevel}_for_power.v text/html 2010-08-18T05:56:33+00:00 http://www.pythonclub.org/vlsi/icc/write-verilog?rev=1282110993&do=diff Post Route Write Verilog Write verilog for STA: set dir . set topLevel zx211000_htm set version 0818_1320 ###### Name changes ## using icc native command (extra rule for some LSI legacy tools) define_name_rules verilog -case_insensitive change_names -hierarchy -rules verilog -verbose write_verilog -no_unconnected_cells ${dir}/${topLevel}.${version}.v