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interview:cmos_circuits_design_faq

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 — interview:cmos_circuits_design_faq [2011/04/29 07:50] (当前版本) 行 1: 行 1: + ====== CMOS Circuits Design FAQ  ====== + 1Q: Give the expression for CMOS switching power dissipation + + Given a frequency f for low-to-high output transitions,​ the power drawn from the supply is C*Vdd*Vdd*f + + 2Q: For CMOS logic, give the various techniques you know to minimize power consumption + + Reduce transistor width, increase threshold voltage, reduce supply voltage, substrate biasing + + 3Q: What are the approximate values for MOSFET drain to source resistance in different modes ? + + Ron = 100 Ohm, Roff > 5 MOhm + + 4Q: What should be done to the threshold voltage of CMOS to reduce the subthreshold leakage current ? + + Threshold voltage should be increased to reduce subthreshold current. + + 5Q: What is a MOSFET channel length modulation ? + + With drain-to-source voltage drop increase, the depletion region at the drain junction grows reducing the efffective channel length. As a result drain-to-source current increases with the associated voltage drop (non-ideal current source in a saturation mode). Devices with bigger channel length are used whenever high-impedance current source is required. + + 6Q: What is a MOSFET body effect ? + + Body effect caused by the increase in source to substrate voltage drop and therefore increase in threshold voltage of a MOS devices usually due to the their serial connection which results in lower currents and slower circuits performance. + + 7Q: Why don’t we use just one NMOS or PMOS transistor as a transmission gate ? + + Transmission gate has better noise margin vs. single pass transistor. Also transmission gate is more efficient to implement some complex logic (XOR, MX, DMX). + + 8Q: Explain sizing of the inverter + + In invertor transistor gates usually sized as 2:1 (p:n) due to the mobility factor (pmos mobility is half of nmos). + + 9Q: Draw a transistor level two input NAND gate. Explain its sizing for equal rise and fall times + + For the equal rise and fall time, transistors sized as 4:1 (p:n) + + 10Q: How do you size NMOS and PMOS transistors to increase the threshold voltage ? + + Threshold voltage is proportional to the channel length i.e. larger channel length means higher threshold voltage and lower leakage power. + + 11Q: Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output ? + + The transistor with the latest arrival time at the gate should be kept near the output to minimize delay. + + 12Q: In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width ? + + To reduce parasitic effects.
interview/cmos_circuits_design_faq.txt · 最后更改: 2011/04/29 07:50 (外部编辑)

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