vlsi:icc:frame
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vlsi:icc:frame [2011/12/09 15:01] (当前版本) |
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| + | ====== Create Frame View ====== | ||
| + | <code> | ||
| + | create_macro_fram -library ${design_vars(mw_lib)} -cell_name ${design_vars(subblks_ics)} \ | ||
| + | -routing_blockage_output_layer metBlk \ | ||
| + | -extract_blockage_by_merge_with_threshold { \ | ||
| + | m7 0 0 m8 0 0 m9 0 0} | ||
| + | </code> | ||
| + | |||
| + | <code> | ||
| + | ########## make size clock ports tcl in fram/cell view ################### | ||
| + | proc maketcl {} { | ||
| + | global width | ||
| + | global length | ||
| + | set ports_file ./p.out | ||
| + | set portslist [open $ports_file a+] | ||
| + | foreach_in_collection sauce [filter_collection [get_attribute [get_clocks] sources -quiet] "object_class == port"] { | ||
| + | set coord [get_attribute $sauce bbox] | ||
| + | set low_x [expr [lindex [lindex $coord 0] 0]] | ||
| + | set low_y [expr [lindex [lindex $coord 0] 1]] | ||
| + | set high_x [expr [lindex [lindex $coord 1] 0]] | ||
| + | set high_y [expr [lindex [lindex $coord 1] 1]] | ||
| + | set direction [get_attribute [get_terminals -of $sauce] access_direction] | ||
| + | if {$direction == "Left"} { | ||
| + | set M3_low_y [expr $low_y - $width] | ||
| + | set M3_high_x [expr $high_x + $length] | ||
| + | set M3_high_y [expr $high_y + $width] | ||
| + | puts $portslist "set_undoable_attribute \[get_terminals [get_attr $sauce name]\] bbox \"$low_x $M3_low_y $M3_high_x $M3_high_y\"" | ||
| + | } elseif {$direction == "Right"} { | ||
| + | set M3_low_y [expr $low_y - $width] | ||
| + | set M3_low_x [expr $low_x - $length] | ||
| + | set M3_high_y [expr $high_y + $width] | ||
| + | puts $portslist "set_undoable_attribute \[get_terminals [get_attr $sauce name]\] bbox \"$M3_low_x $M3_low_y $high_x $M3_high_y\"" | ||
| + | } elseif {$direction == "Down"} { | ||
| + | set M4_low_x [expr $low_x - $width] | ||
| + | set M4_high_x [expr $high_x + $width] | ||
| + | set M4_high_y [expr $high_y + $length] | ||
| + | puts $portslist "set_undoable_attribute \[get_terminals [get_attr $sauce name]\] bbox \"$M4_low_x $low_y $M4_high_x $M4_high_y\"" | ||
| + | } elseif {$direction == "Top"} { | ||
| + | set M4_low_x [expr $low_x - $width] | ||
| + | set M4_high_x [expr $high_x + $width] | ||
| + | set M4_low_y [expr $high_y - $length] | ||
| + | puts $portslist "set_undoable_attribute \[get_terminals [get_attr $sauce name]\] bbox \"$M4_low_x $M4_low_y $M4_high_x $high_y\"" | ||
| + | } | ||
| + | } | ||
| + | close $portslist | ||
| + | } | ||
| + | ############# main procedure ############################################### | ||
| + | sh rm -rf p.out | ||
| + | #### sizeup X4 | ||
| + | set width 0.105 | ||
| + | set length 0.21 | ||
| + | maketcl | ||
| + | #in cellview | ||
| + | source p.out | ||
| + | sh rm -rf p.out | ||
| + | #### sizedown X2 | ||
| + | set width -0.105 | ||
| + | set length -0.21 | ||
| + | maketcl | ||
| + | save_mw_cel -as ${mw_topLevel} | ||
| + | create_macro_fram -library ${mw_topLevel}.mwlib -cell_name ${mw_topLevel} \ | ||
| + | -routing_blockage_output_layer metBlk \ | ||
| + | -extract_blockage_by_merge_with_threshold {\ | ||
| + | m8 0 0 m9 0 0 m10 0 0} | ||
| + | open_mw_cel ${mw_topLevel}.FRAM | ||
| + | #in framview | ||
| + | source p.out | ||
| + | save_mw_cel ${mw_topLevel}.FRAM | ||
| + | close_mw_cel ${mw_topLevel}.FRAM | ||
| + | #in cellview | ||
| + | source p.out | ||
| + | </code> | ||
vlsi/icc/frame.txt · 最后更改: 2011/12/09 15:01 (外部编辑)
除额外注明的地方外，本维基上的内容按下列许可协议发布： CC Attribution-Share Alike 4.0 International
