vlsi:icc:write-verilog
差别
这里会显示出您选择的修订版和当前版本之间的差别。
| — |
vlsi:icc:write-verilog [2010/08/18 05:56] (当前版本) |
||
|---|---|---|---|
| 行 1: | 行 1: | ||
| + | ====== Post Route Write Verilog ====== | ||
| + | |||
| + | Write verilog for STA: | ||
| + | |||
| + | <code tcl> | ||
| + | set dir . | ||
| + | set topLevel zx211000_htm | ||
| + | set version 0818_1320 | ||
| + | |||
| + | ###### Name changes | ||
| + | ## using icc native command (extra rule for some LSI legacy tools) | ||
| + | define_name_rules verilog -case_insensitive | ||
| + | change_names -hierarchy -rules verilog -verbose | ||
| + | write_verilog -no_unconnected_cells ${dir}/${topLevel}.${version}.v | ||
| + | </code> | ||
vlsi/icc/write-verilog.txt · 最后更改: 2010/08/18 05:56 (外部编辑)
除额外注明的地方外，本维基上的内容按下列许可协议发布： CC Attribution-Share Alike 4.0 International
