做Top STA或Power分析的时候，需要用到Top的Verilog Netlist，但是在DFT的时候没有把所有的模块都uniquify， ICC在做优化的时候会在模块上面加port/pin，所以在Top读网表的时候会模块定义会有冲突。写了个脚本，给各个模块加了个前缀，解决了这个问题。

#! /tools/cfr/bin/python
 
import re
import os
import sys
import sets
 
def get_all_module_names(lines):
  patt = """^module ([^ ]*)"""
  module_names = []
  for line in lines:
    if not line: continue
    module_name = re.findall(patt, line)
    if module_name:
      module_name = "".join(module_name)
      module_names.append(module_name)
  return module_names
 
def prefix_module_names(lines, module_names, prefix, fixed_module_names):
  new_lines = []
  module_name_set = sets.Set(module_names)
  patt_instance = """^([A-Za-z0-9_]*)\s[A-Za-z0-9_]*\s\("""
  patt_module = """^module\s([^\s]*)\s\("""
  for line in lines:
    if not line.strip():
      new_lines.append(line)
      continue
    new_line = line
    module_name = re.findall(patt_instance, line)
    if module_name:
      module_name = "".join(module_name)
      if module_name in fixed_module_names:
        pass
      elif module_name in module_name_set:
        new_line = prefix + line
 
    module_name = re.findall(patt_module, line)
    if module_name:
      module_name = "".join(module_name)
      if module_name in fixed_module_names:
        pass
      else:
        new_line = "module " + prefix + line[len("module "):]
    new_lines.append(new_line)
  return new_lines
 
if __name__=="__main__":
 
  verilog_dir = "/home/zx211100/users/dongu/design_data/netlist/TDH2"
  verilog_files = [
    ("pre1_", "cw004265_1_0_wrapper_dcap.v",),
    ("pre2_", "ddr1_top_wrapper_dcap.v",),
    ("pre3_", "ddr2_top_wrapper_dcap.v",),
    ("pre4_", "dlp_spu_dcap.v",),
    ("pre5_", "ics_top_dcap.v",),
    ("pre6_", "ramplus_c_38400x1024_dcap.v",),
    ("pre7_", "srio_top_wrapper_dcap.v",),
    ("pre8_", "uld_top_dcap.v",),
    ("pre9_", "ulp_top_dcap.v",),
    ]
  fixed_module_names = [
    "cw004265_1_0_wrapper",
    "ddr1_top_wrapper",
    "ics_top",
    "ramplus_c_38400x1024",
    "ddr2_top_wrapper",
    "dlp_spu",
    "srio_top_wrapper",
    "uld_top",
    "ulp_top",
    "cw000523_1_0",
    ]
  for prefix, v in verilog_files:
    print "Proecess %s" % v
    v_file = os.path.join(verilog_dir, v)
    lines = open(v_file, 'r').readlines()
    module_names = get_all_module_names(lines)
    new_lines = prefix_module_names(lines, module_names, prefix, fixed_module_names)
    v_new = "".join(new_lines)
    new_name = v_file + 'p'
    open(new_name, 'w').write(v_new) 
    #break