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vlsi:spyglass:lc-usage

Spyglass Lib Complier Usage

Usage:

  spyglass_lc       <options> -gateslib <gateslib source file name>
                    [-plib <plib source file name>] [-lef <lef source file name>]


  spyglass_lc  -usage            show the standard option set.



All SpyGlass Library Compiler options can be supplied in a command file as follows.
  spyglass_lc  -f <command_filename>

-f files can be nested and mixed with command line options.


OPTION DETAILS:

Commonly Used Options:
=====================

    -gateslib <lib-file>     Specifies the Liberty format Cell library file
                             to be loaded.

    -plib <plib-file>        Specifies PLIB library files.

    -lef <lef-file>          Specifies LEF library files.

    -outsglib <outputsglib-filename>
                             Specifies an output sglib file name. By default,
                             the output sglib file name is <lib>.sglib for single 
                             <lib> file, and aggregate_lib.sglib for multiple 
                             <lib> files.
 
    -decompile_lib_models    Decompiles the Functional View of Gate Library
                             Cells into <outputsglib-filename>_spyglass_lc.v file in
                             Verilog HDL format. Only those cells are
                             decompiled for which there were no user-supplied
                             definitions.

    -use_lib_models          Gives preference to Gates Library (.lib) definition
                             over user supplied definition for a cell while
                             creating its functional view.  By default, SpyGlass
                             Library Compiler gives higher priority to user
                             supplied definition.

    -wdir 'work_dir_path'    Specify the directory to be used for keeping
                             all SpyGlass Library Compiler output files,
                             including .vdb, .log .  The default is current
                             working directory.

    -vdbfile <file.vdb>      Define the violation database file -
                             The default is $(wdirpath)/spyglass_lc_<lib_name>.vdb

    -logfile <file.log>      Define the log file -
                             The default is $(wdirpath)/spyglass_lc_<libname>.log

    -report <reporttype>     When analysis has completed, call the report
                             generator for the specified <reporttype>.
                             If this option is not specified then `default'
                             report is generated.

    -waiver <waiver-file>    Specifies the waivers constraints which can be
                             used to selectively waive violations generated
                             during .lib parsing.

    -ignorerules 'rule_name' Rule or group name to be ignored. This is helpful
                             to skip all violations of given LIBWRN or LIBINFO
                             which are generated during .lib parsing.


Perl-Related Options:

    -f <file.f>              Commands are taken from the file;
                             one option per line (with an optional value).
                             Lines beginning with // are ignored.

    -I<directory>            SpyGlass Library Compiler will first attempt to
                             find scripts ,and files required from scripts,
                             in the specified directory, before searching in
                             default locations (specifically under
                             SPYGLASS_HOME/lib and auxi).
                             Multiple -I options may be specified and will
                             be searched in the specified order.


HDL Common Options:
==================

    -param {<key=value>}     Overrides the value of VHDL generics or Verilog 
                             Parameters used in the design. 'key' should be 
                             <ent-name>.<gen-name> or <module-name>.<param-name>.

    -pragma <pragma_name>    Specify a prefix for synthesis pragmas;
                             the default is `synopsys' for Verilog source, and
                             both 'synopsys' and 'pragma' for VHDL source.
                             this option can be specified multiple times.
                             Use '-pragma nopragma' to disable all pragma.

   -lib <logical> <physical> Specify the logical-to-physical mapping for
                             referenced libraries; the physical locations must
                             exist but may be multiply used. For example,
                                -lib STD  ~/SPYGLASS_HOME/vhdl_libs/STD
                                -lib IEEE ~/SPYGLASS_HOME/vhdl_libs/IEEE

    -work 'name'             Use the logical library `NAME' for compilation
                             the default value is `WORK'

    -remove_work             Forces cleanup of work directory, before starting
                             the design parsing.


VHDL-Specific Options:
=====================

    -87                      Check for IEEE-1076 VHDL-87 compliance.

    -sort                    Sort the files before analyzing;
                             this is useful when specifying `*.vhd'

    -disable_sort            Disable the effect of -sort if -sort has been
                             enabled through configuration file.

    -hdlin_translate_off_skip_text  completely ignore the VHDL code between
                                    translate_off/translate_on pragma block.

    -hdlin_synthesis_off_skip_text  completely ignore the VHDL code between
                                    synthesis_off/synthesis_on pragma block.                                    
    -relax_hdl_parsing       Performs relaxed VHDL semantic checking 


Verilog-Specific Options:
========================

    +define+<var1>+...       Add the specified macro definitions.

    +incdir+<path1>+...      Search specified paths for include files.

    +libext+<ext1>...        Specify library directory file extensions.

    -ovi2                    Analyze for OVI 2.0 compatibility.

    -v <file>                Specify a library file.

    -y <directory>           Specify a library directory.

    -show_lib                Generates info as to which modules are loaded
                             from -v, -y library along with the library name.
    
    -disablev2k              Disable parsing of Verilog 2000/2001 constructs.
                             It has been enabled by default.

    -enableSV                Enable parsing of System Verilog constructs.
                             The default is to give error for System Verilog
                             constructs.

    +resetall                Resets Verilog compiler directive 'default_nettype' 
                             to language default which is 'wire'. 
                             Other Verilog compiler directives are not reset 
                             currently by this option.
                             It is useful while analyzing multiple design files 
                             where user doesn't want to specify this default 
                             in each of these files.


Other SpyGlass Library Compiler Optional Features:
=================================================

    -mthresh <number>        Specify a bit-count threshold for the compilation
                             of memories. Above the threshold, memories will
                             not be compiled (they are treated as black boxes).
                             The default value is 4096 bits.
                             Also see: -handlememory

    -handlememory            Enables special processing for design containing
                             large size memory instances.

    -include_tao_data        Enables the preparation of timing and optimization
                             (tao) data. The generated sglib file contains the
                             prepared tao data.

    -include_opt_data        Enables preparation of advanced optimized data.
                             The generated data is stored in sglib to use 
                             in power estimation flow for faster processing.

    -LICENSEDEBUG            Generates license checkout related debugging
                             information in the logfile.

    -DEBUG                   Generates additional debugging information in
                             the logfile.

    -enable_cmdline_debug    Generates a Command-line processing debug log in
                             wdir. The debug log contains the tracing of the 
                             internal processing of user-specified command-line
                             options done by SpyGlass in both BATCH and Console
                             mode. 
SpyGlass Exit Code 0 (Informational command executed, rule-checking not done)
vlsi/spyglass/lc-usage.txt · 最后更改: 2012/11/20 06:11 (外部编辑)