这里会显示出您选择的修订版和当前版本之间的差别。
两侧同时换到之前的修订记录 前一修订版 | 前一修订版 | ||
vlsi:start [2011/04/29 06:01] |
vlsi:start [2017/03/31 09:07] (当前版本) admin [Models] |
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- | ====== Backend Design ====== | + | ====== ASIC Backend Design ====== |
===== Flow Scripts ===== | ===== Flow Scripts ===== | ||
- | * [[vlsi:icc:flow]] | + | * [[vlsi:tools:synopsys]] |
+ | * [[vlsi:icc:start]] | ||
+ | * [[vlsi:pt:start]] | ||
+ | * [[vlsi:dc:start]] | ||
+ | * [[vlsi:redhawk:start]] | ||
+ | |||
+ | * [[vlsi:star-rc:start]] | ||
+ | * [[vlsi:calibre:start]] | ||
===== VLSI Basic Concept ===== | ===== VLSI Basic Concept ===== | ||
* [[vlsi:basic:unate]] | * [[vlsi:basic:unate]] | ||
+ | * [[vlsi:verilog:start]] | ||
+ | * [[vlsi:basic:fail]] | ||
===== Models ===== | ===== Models ===== | ||
* [[vlsi:models:wire-load-model]] | * [[vlsi:models:wire-load-model]] | ||
* [[vlsi:models:etm]] | * [[vlsi:models:etm]] | ||
+ | * [[vlsi:models:aocv]] | ||
===== EDA Tools ===== | ===== EDA Tools ===== | ||
+ | * [[vlsi:spyglass:start]] | ||
- | * [[vlsi:tools:synopsys]] | ||
- | * [[vlsi:icc:start]] | ||
- | * [[vlsi:star-rc:start]] | ||
===== IC Design Interview Questoins ===== | ===== IC Design Interview Questoins ===== | ||
行 25: | 行 33: | ||
* For more VLSI information, please visit http://www.truevue.org/vlsi | * For more VLSI information, please visit http://www.truevue.org/vlsi | ||
+ | ===== Scripts Utility===== | ||
+ | * [[vlsi:scripts:prefix-verilog-module]] | ||
+ | * [[vlsi:scripts:create-lib-from-verilog]] | ||
+ | * [[vlsi:scripts:get-block-size]] |